1. Field of the Invention
The present invention relates to a memory and a method of fabricating the same, and more particularly to a flash memory and a method of fabricating the same.
2. Description of Related Art
A non-volatile memory allows multiple data writing, reading and erasing operations. Moreover, the stored data are retained even after the power of a device has been shut down. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipments. Generally, a typical memory device includes a stacked gate structure constituted by a floating gate and a control gate. The floating gate is disposed between the control gate and a substrate and is in a floating state. The control gates are connected to word lines. Moreover, a tunneling dielectric layer is disposed between the substrate and the floating gates, and a inter-gate dielectric layer is disposed between the floating gates and the control gates.
Conventionally, the floating gates are disposed between isolation structures, and surfaces of the floating gates are, for instance, aligned with surfaces of the isolation structures. Therefore, area of the exposed surfaces of the floating gates is increased by removing a portion of the isolation structures disposed between the floating gates. Consequently, contact areas between the floating gates and the control gates are increased so as to enhance a gate-coupling ratio (GCR).
However, the memory device includes a cell region and a periphery region. In order to remove a portion of the isolation structures between the floating gates in the cell region, a portion of the isolation structures in the periphery region is usually removed simultaneously. In the periphery region, a gate dielectric layer on the substrate disposed between the isolation structures is exposed when isolation structures are excessively removed. As a result, the gate dielectric layer is degraded in the following etching process and cleansing process, thereby affecting electrical properties of devices in the periphery region. In addition, a inter-gate dielectric layer is formed on the substrate after a portion of isolation structures is removed. After that, the inter-gate dielectric layer and the floating gates in the periphery region are removed subsequently. If a height difference between surfaces of the isolation structures in the periphery region and surfaces of the floating gates is great, the subsequent etching process for removing the inter-gate dielectric layer and the floating gates in the periphery region will be difficult to proceed due to a spacer effect.
Hence, how to remove a portion of the isolation structures in the cell region and the periphery region to enhance the GCR of the memory device and maintain excellent electrical property is a critical issue to be solved urgently.